1. Technical Field
The present invention relates to sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, useful in low-supply-voltage technologies.
Specifically, the invention relates to sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, said sensing circuitry comprising a sense amplifier having a first sensing-circuit portion connected to a cell to be read and a second reference-load-circuit portion connected to a reference generator.
The invention relates, particularly but not exclusively, to circuitry for sensing the state of memory cells in embedded applications with low supply voltages, this description making reference to that field of application for convenience of illustration only.
2. Prior Art
As is well known, semiconductor memories are organized in cell arrays set up as rows or wordlines and columns or bitlines.
Each cell has essentially a floating-gate transistor, which also has drain and source terminals. The floating gate is formed on top of a semiconductor substrate and separated from the substrate by a thin layer of gate oxide. A control gate is coupled capacitively to the floating gate through a dielectric layer, and metal electrodes are provided to contact the drain, source, and control gate so that predetermined voltage values can be applied the memory cell.
The cells in one wordline share an electric line driving their respective control gates (directly in flash memories, and indirectly through a pass transistor in EEPROMs), while the cells in one bitline have the drain terminal in common.
The state of the cell is sensed, i.e. the information stored in it is xe2x80x9creadxe2x80x9d, by means of sensing circuitry.
The reading is effected by sensing a current value that flows through a cell to be read, at a preset bias through an amplifying circuit, in particular a sense amplifier.
The sense amplifier is used to bias the cell drain terminal, as well as to read the cell state. The drain terminal is accessed through the bitline, which is, as mentioned before, a metal line interconnecting (directly in flash memories, and indirectly through a select transistor in EEPROMs) the drain terminals of all the cells in one column of the array. Thus, the bitline has an amount of capacitance that is proportionate to the vertical dimension of the array and must be precharged at the voltage level to which the drain terminal of a cell being read is to be biased. The precharging is also performed through the sense amplifier.
Recent generations of memories are designed to provide shorter access times along with larger storage capacities (i.e., number of cells) with supply voltages that are specified at ever lower levels.
Accordingly, faster sense amplifiers at low supply voltages are in demand.
A first prior approach to satisfy this demand is illustrated by a conventional sense amplifier SA1 for use in smart card applications, as shown in FIG. 1.
In particular, the sense amplifier SA1 has a first circuit portion or sensing portion 1 connected between a voltage supply Vdd and ground GND.
The sensing portion 1 has a first leg, comprising a cascade of a PMOS transistor Mmir10 and an NMOS transistor M10. The sensing portion 1 also has a second leg 3 comprising a native transistor NAT1, which is a low-threshold transistor connected between the voltage supply Vdd and a first node A.
The control terminal of the native transistor NAT1 is connected to an interconnection node MAT, itself connecting the transistors Mmir10 and M10 together. The control terminal of transistor M10 is connected to the node A. A resistor R is connected between the node A and a node BUS1.
This node BUS1 is connected, through a decode circuit N1, to the drain terminal of a cell 4 whose state is to be sensed.
At steady state, the current flowing through the cell 4 also flows through the transistor NAT1. Since the voltage level at node A is dependent on the size of transistor M10 and the bias current to transistor NAT1, the node MAT is brought to a level such that a voltage VGS (VMAT-VA) at transistor NAT1 will cause a current I flowing through the transistor M10 to equal the current ICELL1 flowing through the cell 4. Therefore, transistor NAT1 effects a current-to-voltage conversion.
The sense amplifier SA1 further comprises a second circuit portion, or reference portion 5, connected between the voltage supply and ground GND. The reference portion 5 has a first leg 7 comprising a cascade of a PMOS transistor Mmir20 and an NMOS transistor M2. The reference portion 5 also has a second leg 6 comprising a native transistor NAT2 connected between the voltage supply Vdd and a node B.
The control terminal of the native transistor NAT2 is connected to a node REF2, itself connecting the transistors Mmir20 and M2 together. The control terminal of transistor M2 is connected to the node B, which also has a reference cell 8 connected to it.
This reference portion 5 performs dynamically like the first sensing portion 1. The transistor NAT2 effects then a current-to-voltage conversion, with the voltage level at node REF2 being set by a given reference current IREF2.
If more current flows through the cell 4 to be read than through the reference cell 8, then node MAT is at a higher voltage level than node REF2, whereas if the current through the cell 4 to be read is smaller than the current through the reference cell 8, then node MAT is brought at steady state down to a lower voltage level than node REF2.
By comparing these two nodes, MAT and REF2, in a voltage comparator (not shown because conventional) the state of the cell 4 can be determined, the state of the reference cell 8 being known beforehand.
While being advantageous in several aspects, this first approach has shortcomings. The voltage difference between the voltage supply Vdd and ground GND is equal to the sum of the voltage Vds at PMOS Mmir10, voltage Vgs at the native (low-threshold) transistor NAT1, and voltage Vgs at the inverter M10, namely:
Vdd=VdsMmir10+VgsNAT1+VgsM10xe2x80x83xe2x80x83(1)
Equation (1) above becomes a fairly critical one with low supply voltages.
Another shortcoming comes from the bound placed on the size of transistors M10 and NAT1. Transistor M10, in fact, cannot be highly conductive because the bitline bias is dependent on its voltage Vgs.
As best seen with reference to FIG. 2, however, the I-V characteristics of MOS transistors diverge from each other as temperature varies, except around a specific value of the voltage Vgs. This value of Vgs is the value at which temperature compensation is achieved between the effects of diminishing threshold as temperature increases (that depresses Vgs) and diminishing current gain (that increases the voltage Vgs for a given bias current I).
Nor can transistor M10 deviate substantially from that value of the voltage Vgs. For example, it may be about 740 mV, to prevent the bitline bias from changing substantially with temperature.
Transistor NAT1 cannot be highly conductive because the sensitivity S of the sense amplifier is dependent on it, as follows:
S=|dVMAT/dICELL1|=1/gmNAT1xe2x80x83xe2x80x83(2)
where,
VMAT is the voltage at node MAT;
ICELL1 is the current through the cell 4 to be read; and
gmBAT1 is the transconductance of the native transistor NAT1.
For instance, assuming the circuit of FIG. 1 to have been dimensioned for sensitivity Sxe2x89xa725 mV/uA and the voltage difference at node BUS1 (xcex94Vbus1)xe2x89xa660 mV at varying temperatures between xe2x88x9240xc2x0 and 125xc2x0 C., a current ICELL1=3 uA is sufficient to bring the node MAT to about 1.1V, as shown in FIG. 3, and at Vdd=1.2V, the PMOS transistor Mmir10 has Vds=100 mV and its mirrored current I goes to 7.3 uA, from 8 uA, as shown in FIG. 4.
The sensing circuit SA1 is also used to precharge the bitline. Nodes MAT and REF are preset at the supply voltage Vdd and the ground voltage GND, respectively. At power-on of the sensing circuit SA1, node BUS1 is discharged, i.e. is same as GND, and the voltage Vgs at the native transistor NAT1 is initially same as Vdd. At this stage, transistor NAT1 allows the bitline to be precharged with much overdrive and, therefore, a large current ICELL1. BUS1, while under charge, will tend toward the bias voltage set by transistor M10 functioning as an inverter, and by its bias current I. Node MAT is then brought to a sufficient level for the current needed by the cell 4 to be read to flow through transistor NAT1.
Therefore, a need has arisen for a sensing circuit that can be operated on low supply voltages and that overcomes problems that besets prior-art sensing circuits.
In one aspect of the invention, sensing circuitry includes two current/voltage conversion blocks respectively connected to a memory cell to be read and to a reference cell, said blocks being connected to a single bias and precharge block such that the bias block is not in the conductive path between the voltage supply Vdd and ground GND of the individual conversion blocks.
Features and advantages of the sensing circuit according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.